State machine, semiconductor device and electronic equipment

ABSTRACT

A state machine operates in synchronization with a reference clock signal ( 110 ) to switch between n numbers of states and maintain any one of these states. Every time a condition for transition to each of the n numbers of states is satisfied, a signal output circuit ( 100 ) makes one of n numbers of transition condition satisfying signals ( 111 W,  111 Z,  111 Y . . . ) active and outputs it. One of a plurality of D-type flip-flops ( 101 - 1, 101 - 2, 101 - k  . . . ) makes active any one of nu numbers of state signals (W, Z, Y . . . ) indicating the corresponding n numbers of states, and holds the corresponding one state. A synchronization pulse generation circuit ( 102 ) generates a one-shot synchronization pulse signal ( 112 ) in synchronization with the reference clock signal ( 110 ), when a transition condition for transition to one state is satisfied. When a one-shot synchronization pulse signal ( 112 ) is input to the D-type flip-flop ( 101 - k ) and also the condition for transition to state Y has been satisfied, the state Y is held during the period from after the establishment of the condition for transition to the state Y, until a condition for transition to another state such as W or Z is satisfied.

TECHNICAL FIELD

The present invention concerns a logic circuit technology and relates toa state machine operating in synchronization, a semiconductor device andelectronic equipment.

BACKGROUND OF ART

A state machine has a plurality of states and transitions between thesestates occur when a condition for transition from one state to anotherstate is satisfied. Most of state machines within a system, operate attimings that are synchronized with the same reference clock signal, andeach state machine operates to represent only one state during the sameperiod, while mutually exchanging signals. With a state machine thatbranches to at least two states depending on conditions, particularlyduring a transition from a certain state to another state, it iscustomary to have one flip-flop for one state, in order to prevent anystatic hazard in the circuitry that forms the state machine.

A state machine without branches is equivalent to a binary counter, andit decodes states held in k numbers of flip-flops to create a number ofstates n that is greater than k, without causing any static hazard, in amanner similar to a well-known Gray code counter. In a circuit designedto be completely synchronous, states hazard is no problem provided thatprescribed conditions are satisfied, such as the state signals of thestate machine are not used as trigger signals for other circuits. Insuch a case, the states of k numbers of flip-flops can be decoded tocreate n numbers of states, where n is a larger number than k.

An example of a state transition diagram of a state machine, given inFIGS. 14 to 6 of the ISO/IEC8802-3 Standard, has been simplified and isshown as FIG. 12 herein. When a transition condition is satisfied, thisstate machine acquires any one of state from five states 401 to 406, viatransitions 410 to 420. For example, the condition that causes thetransition 412 is “link_loss_timer_done*RD=idle*link_test_rcv=false”, inaccordance with the standard. When that condition is satisfied when thecurrent state is the state 401, the transition 412 is executed to switchto the state 402.

A partial extract of the state transition diagram of the state machineis shown in FIG. 13, centered on a state Y and showing only transitionsto that state and transitions from that state. An example of aconfiguration by which the state Y is set by one flip-flop is shown inFIG. 14.

FIG. 14 shown an example in which each state is set by a single D-typeflip-flop (hereinafter abbreviated to D-type F.F.). The state Y can beobtained at a Q output terminal of a D-type F.F. 501-k by inputting to aC input terminal thereof a reference clock signal 110 via a buffer 503and inputting to a D input terminal thereof a signal that is raised by acondition of “switch to state Y and maintain that state Y”. In otherwords, the transition to the state Y occurs when the condition “stateP×condition a+state Q×condition b” occurs (see FIG. 13). In addition, tomaintain the state Y when the state is currently Y, the condition is“state Y×(−condition c) (−condition d)”, according to FIG. 13. The sumof a condition (transition condition) 111Y for transition to the state Yand a condition (holding condition) 612Y for holding the state Y isobtained by an OR gate 502-k and is input to the D input terminal of theD-type F.F. 501-k. The transition condition 111Y and the holdingcondition 612Y are obtained by using AND gates 504 to 507 shown in FIG.15.

Operating waveforms of the state machine of FIG. 14 are shown in FIG.16. The reference clock signal 110 is generated throughout all operatingperiods and the transition condition 111Y for transition to the state Ybecomes true at a time a. At this point, either the condition a issatisfied within the state P or the condition b is satisfied within thestate Q. Since the transition condition 111Y is modified by a certaindelay with respect to the timing of the system clock, the state Ybecomes true at a time b, which is the time of the next clock.Subsequently, a transition condition 111W for transition to the state Wbecomes true at a time c. At this point, a condition d is satisfiedwithin the state Y. The holding condition 612Y for the state Y remainsactive in the state Y while there is no condition for the transitionfrom the state Y. In other words, the holding condition 612Y is heldtrue by ensuring that neither the condition c nor the condition d issatisfied during the period from the time b to the time c. The operationof the holding condition 612Y is similar to that when a condition fortransition from the state Y to a sate Z is satisfied, by satisfying thecondition c when in the state Y, at the time c. The state Y is madefalse at a time d by the transition condition 612Y going false at thetime c.

An example of a configuration in which one state is set by one JK-typeflip-flop (hereinafter abbreviated to JK-type F.F.) is shown in FIG. 17.The state Y can be obtained at a Q output terminal of a JK-type F.F.521-k by inputting the reference clock signal 110 to a C input terminalthereof, the transition condition 111Y for transition to the state Y toa first input terminal thereof, and the transition condition 212Y fortransition to another state from the state Y to a second input terminalthereof. The transition condition 111Y for transition to the state Y isequivalent to that for a D-type F.F., and the transition condition 212Yfor transition to another state from the state Y is “state Y×conditionc+state Y×condition d”, according to FIG. 13. The transition condition111Y and the transition condition 212Y are obtained by AND gates 522 to525 and OR gates 526 and 527, as shown in FIG. 18.

Operational waveforms of the state machine of FIG. 16 are shown in FIG.19. The transition condition 111Y for transition to the state Y becomestrue at the time a. At this point, either the condition a is satisfiedwithin the state P or the condition b is satisfied within the state Q.This makes the state Y true at the time b. The transition condition fromthe state Y subsequently becomes true at the time c. At this point,either the condition c is satisfied within the state Y, or the conditiond is satisfied. This makes the state Y become false at the time d.

In accordance with these conventional techniques, a large number ofstate machines which configure the system must be operatedsimultaneously at the clock timing required by the system, which raisesa problem in that the power consumption increases. Any increase in thenumber of state machines and the number of state machine's statesnecessitates increased number of components, and the clock is need to bedriven by a corresponding amount. In addition, in order to drive theclocks of a large number of flip-flops simultaneously, a buffercomponent having a large drive capability is necessary. The powerconsumption problem is dramatic in a system in which state transitionconditions occur at a far longer separation than the reference clock,such as a state machine for a link integrity test as set by theISO/IEC8802-3 Standard and shown in FIG. 12.

In the state machine of FIG. 12, transition conditions satisfyfrequently, on the order of microseconds to seconds with respect to thereference clock signal of 10 MHz. In that case, driving all of theflip-flops at the 10 MHz of the reference clock signal means that powerlosses are great when they are not operating.

In addition, the conventional technique necessitates that the conditionsfor transition to the various states and either the conditions formaintaining those states or conditions for transition to another statefrom those states are input the flip-flops representing the states ofthe state machine. This makes the state machine more complicated andnecessitates a large number of circuit components. A transitioncondition to a certain state is also a transition condition from anotherstate, and signals indicating similar conditions can be used in acomplicated fashion to indicate other states. As a result, theredundancy of the circuitry increases, which makes the circuitry morecomplicated and is a factor in increasing the number of debugging andmaintenance steps.

An objective of the present invention is to provide a state machine, asemiconductor device, and electronic equipment using the same, whichenable a reduction in power consumption.

Another objective of the present invention is to provide a statemachine, a semiconductor device, and electronic equipment using thesame, which enable a reduction in circuit redundancy, simplify thecircuitry accordingly, and which also enable a reduction in the numberof debugging and maintenance steps therefor.

DISCLOSURE OF THE INVENTION

An aspect of the present invention relates to a state machine operatingin synchronization with a reference clock signal and holding any onestate that shifts between n numbers of states, the state machinecomprising:

signal output means for activating and outputting any one of n numbersof transition condition satisfying signals, every time a condition fortransition to any of the n numbers of states is satisfied;

n numbers of state holding means provided in correspondence to the nnumber of states, for outputting n numbers of state signals representingthe corresponding n numbers of states, any one of the n numbers of statesignals being activated so as to hold one of the n numbers of states;and

synchronization pulse signal generation means for generating a one-shotsynchronization pulse signal which synchronizes with the reference clocksignal, when the condition for transition to any one of the states issatisfied,

wherein the one-shot synchronization pulse signal is input in common toall of the n numbers of state holding means, and any one of the stateholding means corresponding to any one the states for which a transitioncondition is satisfied makes corresponding one of the state signalsactive, during a period from the satisfaction of the condition fortransition to one of the states until the satisfaction of a conditionfor transition to another one of the states.

With this aspect of the invention, the input terminals of the n numbersof state holding means are driven only at the times at which theone-shot synchronization pulse signal is input in common; at all timesthey are not driven at all. It is clear that the component that isalways driven in synchronization with the reference clock signal duringthis time is an input terminal of the synchronization pulse signalgeneration means. It is therefore clear that the power consumed in thedevice of this aspect of the invention is markedly lower than that of aconventional device which operates at all of the timing synchronizedwith the reference clock signal. Moreover, since circuit redundancy canbe reduced because it is not necessary to input holding conditions, thecircuitry is simplified and the effect of reducing the number ofdebugging and maintenance steps can be achieved.

Within this aspect of the invention, the n numbers of state holdingmeans may be configured of first to nth D-type flip-flops. In that case,the n numbers of transition condition satisfying signals may be input tothe data input terminal of the corresponding first to nth D-typeflip-flop. In addition, the synchronization pulse signal that isgenerated by the synchronization pulse signal generation means may beinput to the clock input terminals of all these first to nth D-typeflip-flops. First to nth state signals may be output from data outputterminals of the corresponding first to nth D-type flip-flops.

With such a configuration, it is clear that only transition conditionsatisfying signals for transition to each state are input to the nnumbers of D-type flip-flops, and holding conditions are not necessary.It is therefore clear that the size of circuitry necessary for thedevice of the present invention is markedly smaller than that of theconventional device of FIG. 14.

With this aspect of the invention, the n numbers of state holding meansmay be configured of first to nth JK-type flip-flops. In that case, then numbers of transition condition satisfying signals may be input to thefirst input terminal of the corresponding first to nth JK-typeflip-flop. In addition, signals any one of which is made active bysatisfying a condition for transition to another state from any one ofthe first to nth states may be input to second input terminals of thefirst to nth JK-type flip-flops. Similarly, the synchronization pulsesignal that is generated by the synchronization pulse signal generationmeans may be input to the clock input terminals of all these first tonth JK-type flip-flops. First to nth state signals are output from dataoutput terminals of the corresponding first to nth JK-type flip-flops.

With such a configuration, the n numbers of JK-type flip-flops that holdthe respective states are the same as in the conventional device of FIG.18 in that it is necessary to have transition condition satisfyingsignals for transition to each state and transition conditions fortransition from each state, but they make it possible to achieve amarkedly lower power consumption than that of the conventional device ofFIG. 18 in that the JK-type flip-flops are not driven constantly basedon the reference clock signal.

Another aspect of the present invention relates to a state machineoperating in synchronization with a reference clock signal and holdingany one state that shifts between n numbers of states, the state machinecomprising:

signal output means for outputting k numbers of (where k<n) first to kthcombined transition-condition satisfying signals corresponding to the nnumbers of states, every time there is a change in conditions fortransition to any of the n numbers of states;

synchronization pulse signal generation means for generating a one-shotsynchronization pulse signal which synchronizes with the reference clocksignal, when the condition for transition to one of the states issatisfied;

k numbers of state code holder means for outputting first to kth statecode signals corresponding to the first to kth combinedtransition-condition satisfying signals, based on the first to kthcombined transition-condition satisfying signals and the one-shotsynchronization pulse signal; and

decoding means for decoding the first to kth state code signals that areoutput from the k numbers of state code holder means and generating nmeans of state signals corresponding in a one-to-one manner to the nnumbers of states.

This aspect of the present invention can be applied to a device in whichstate code signals from k numbers of state code holder means configuredof flip-flops or the like are decoded to generate n numbers of statesignals (where n>k). In this case too, it is possible to achieve amarkedly lower power consumption than in the conventional device,because the all of the k numbers of state code holder means are notdriven constantly based on the reference clock signal.

The synchronization pulse signal generation means of the presentinvention may comprise a D-type flip-flop and an AND circuit. A signalthat is made active by any of the first to kth transition conditionsatisfying signals may be input to a data input terminal of the D-typeflip-flop and an inverted signal of the reference clock signal is inputto a clock input terminal thereof. By inputting a data output of theD-type flip-flop and the reference clock signal to the AND circuit, aone-shot synchronization pulse signal may be output from this ANDcircuit every time a transition condition is satisfied.

The present invention may be provided with state-monitoring means fordetecting an abnormality by monitoring the n numbers of states anddetecting an abnormality that is indicated by at least two states beingtrue. After detecting an abnormality, this state-monitoring means resetsthe abnormal state and causes the state machine to return to aprescribed state other than the abnormal state, such as an initialstate.

A further aspect of the present invention relates to a semiconductordevice operating in synchronization with a reference clock signal, suchthat a state of a signal in an (m+1)th operating cycle is determinedbased on a state of a signal within an mth operating cycle, wherein thesemiconductor device comprises n numbers of state machines and at leastone state machine has the configuration described above.

Electronic equipment in accordance with a still further aspect of thepresent invention comprises the above-described semiconductor device.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a circuit diagram of a first embodiment of a state machine inaccordance with the present invention.

FIG. 2 is a circuit diagram of an example of the signal output circuitof FIG. 1;

FIG. 3 is an operational waveform chart of the state machine of FIG. 1;

FIG. 4 is a circuit diagram of a second embodiment of a state machine inaccordance with the present invention;

FIG. 5 is a circuit diagram of part of the configuration of the signaloutput circuit of FIG. 4;

FIG. 6 is an operational waveform chart of the state machine of FIG. 4;

FIG. 7 is a circuit diagram of a third embodiment of a state machine inaccordance with the present invention;

FIG. 8 is a state transition diagram of the state machine of FIG. 7;

FIG. 9 is a circuit diagram of an example of the signal output circuitof FIG. 7;

FIG. 10 is a block diagram of a fourth embodiment of a state machine inaccordance with the present invention;

FIG. 11 is a block diagram of a fifth embodiment of a state machine inaccordance with the present invention;

FIG. 12 shows an example of state transitions;

FIG. 13 shows another example of state transitions;

FIG. 14 is a circuit diagram of a conventional state machine;

FIG. 15 is a circuit diagram of the logic circuit that generates thetransition conditions and holding conditions of FIG. 14;

FIG. 16 is an operational waveform chart of the state machine of FIG.14;

FIG. 17 is a circuit diagram of another conventional state machine;

FIG. 18 is a circuit diagram of the logic circuit that generates thetransition conditions and holding conditions of FIG. 17; and

FIG. 19 is an operational waveform chart of the state machine of FIG.17.

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment

A first embodiment of a state machine in accordance with the presentinvention is shown in FIG. 1. Note that the state machine shown in FIG.1 is set for the various states shown in FIG. 13, so that the states W,Y, and Z in FIG. 1 correspond to the states W, Y, and Z in FIG. 13.

In FIG. 1, this state machine comprises a signal output circuit 100 thatoutputs transition condition satisfying signals 111W, 111Z, 111Y, etc.;D-type F.Fs. 101-1, 101-2, 101-K, . . . acting as state holding meansfor holding each of the various states shown in FIG. 13; and asynchronization pulse generation circuit 102.

An example of the signal output circuit 100 of FIG. 1 is shown in FIG.2. As shown in FIG. 2, this signal output circuit 100 comprises ANDgates 100-1 to 100-4 and an OR gate 100-5. The AND gate 100-1 makes thetransition condition satisfying signal 111W go active (become 1) andoutputs it when both the state Y and a condition d are 1; otherwise itmakes the transition condition satisfying signal 111W be non-active(become 0). Similarly, the AND gate 100-2 makes the transition conditionsatisfying signal 111Z go active (become 1) and outputs it when both thestate Y and a condition c are 1; otherwise it makes the transitioncondition satisfying signal 111Z be non-active (become 0). Furthermore,the AND gates 100-3 and 100-4 and the OR gate 101-5 make the transitioncondition satisfying signal 111Y go active (become 1) and outputs itwhen both the state P and a condition a are 1 or when both the state Qand a condition b are 1; otherwise they make the transition conditionsatisfying signal 111Y be non-active (become 0).

The synchronization pulse generation circuit 102 comprises an AND gate103, an OR gate 104, and a D-type F.F. 105. All of the transitioncondition satisfying signals, including the previously describedtransition condition satisfying signals 111W, 111Z, and 111Y, are inputto the OR gate 104. An inversion signal of a reference clock signal 110is input to a C input terminal of the D-type F.F. 105 and an output ofthe OR gate 104 is input to a D input terminal thereof. An output signal115Q from a Q output terminal of the D-type F.F. 105 is input to the ANDgate 103 together with the reference clock signal 110.

The transition condition satisfying signals 111W, 111Z, . . . 111Y . . .are input to D input terminals (data input terminals) of thecorresponding D-type F.Fs. 100-1, 100-2, . . . 100-k that act as stateholder circuits whereas a synchronization pulse signal 112 that is anoutput of the AND gate 103 in the synchronization pulse generationcircuit 102 is input in common to all the C input terminals (clock inputterminals) thereof.

The operation of the state machine of FIG. 1 will now be described withreference to the timing chart of FIG. 3. FIG. 3 shows the operation of atransition from the state P or the state Q to the state Y, followed byanother transition to the state W.

For a transition from the state P or the state Q to the state Y, it isnecessary to make the transition condition satisfying signal 111Y ofFIGS. 1 and 2 go active. The condition for making the transitioncondition satisfying signal 111Y go active must be to satisfy the logiccondition “stage P×condition a+state Q×condition b”, from FIG. 13. Ifthis logic condition is satisfied, the transition condition satisfyingsignal 111Y that is output by the OR gate 100-5 of FIG. 2 becomes activebetween the times a and c in FIG. 3, and this active signal 111Y isinput to the OR gate 104 and the D-type F.F. 100-k of FIG. 1.

At the same time, the reference clock signal 110 is output continuouslythroughout all the operating periods as shown in FIG. 3. In this case,when the transition condition satisfying signal 111Y becomes active atthe time a in FIG. 3, “1” is input to the D input terminal of the D-typeF.F. 105 through the OR gate 104 of the synchronization pulse generationcircuit 102. An inverted signal of the reference clock signal 110 isinput to the C input terminal of the D-type F.F. 105. Thus “1” appearsat the Q output terminal (data output terminal) of the D-type F.F. 105at a time b at which the reference clock signal 110 next falls (rise ofthe inverted signal thereof) after the time a (see output signal 115Q inFIG. 3).

The value at the Q output terminal of the D-type F.F. 105 is held untilthe reference clock signal 110 next falls (the next rise of the invertedsignal thereof). This makes the synchronization pulse signal 112, whichis at 1 for the width of the half-cycle of the reference clock signal110, appear in synchronization with the reference clock signal 110 atthe time c, from the AND gate 103 to which the output signal 115Q of theD-type F.F. 105 and the reference clock signal 110 are input.

In this case, the D-type F.F. 101-k, to which the activated transitioncondition satisfying signal 111Y is input through the D input terminal,is also inputs the synchronization pulse signal 112 through the c inputterminal during the period in which the transition condition satisfyingsignal 111Y is active, as shown in FIG. 3. Thus a signal that makes thestate Y active is output from the Q output terminal of the D-type F.F.101-k at the time c shown in FIG. 3.

The synchronization pulse signal 112 does not become activesubsequently, so long as no other transition condition satisfying signalsuch as the signal 111W becomes active, thus the Y state is held by theoutput from the Q output terminal of the D-type F.F. 101-k.

However, the transition condition satisfying signal 111Y is modified bya delay with respect to the timing of the system clock (see the brokenline in FIG. 3, for example), so that the state Y becomes true at thetime c only if there is enough delay to ensure a sufficiently long holdtime to maintain the active state before the rise of the synchronizationpulse signal 112.

Now assume in this case that the transition condition satisfying signal111W for transition to the state W becomes true at a time d in FIG. 3.At this point, the condition d is satisfied at the state Y, and thetransition condition satisfying signal 111W that is output from the ANDgate 100-1 of FIG. 2 becomes active. The synchronization pulse signal112 is generated at a time f because the transition condition satisfyingsignal 111W has become active, by the same operation as that whichactivated it at the time c. The state W becomes true at the time f inFIG. 3, by the output from the Q output terminal of the D-type F.F.101-1 to which is input the transition condition satisfying a signal111W at the rise of the synchronization pulse signal 112 at the time f.At this point, the transition condition satisfying signal 111Y isnon-active, so the state Y is false at the time f at which thesynchronization pulse signal 112 becomes active.

It can be seen that while this state machine is operating, the C inputterminals of all of the D-type F.Fs. 101-1, 101-2, . . . 101-K, . . .are driven only at the time c at which the state Y is true and the timef at which the state Y is false; at all other times they are not drivenat all. It is also clear that the components that are always driven insynchronization with the reference clock signal 110 during this time arethe C input terminal of the D-type F.F. 105 and the single inputterminal of the AND gate 103. It is therefore clear that the powerconsumed in the device of this aspect of the present embodiment ismarkedly lower than that of a conventional device in which all of thetiming is in synchronization with the reference clock signal. Moreover,since circuit redundancy can be reduced because it is not necessary toinput holding conditions, the circuitry is simplified and the effect ofreducing the number of debugging and maintenance steps can be achieved.

Each of the D-type F.Fs. 101-1, 101-2, . . . 101-K, . . . that hold thestates inputs only the transition condition satisfying signal fortransition to the corresponding state, so it is clear that it is notnecessary to have holding conditions or conditions for transition fromeach state. It is therefore clear that the size of circuitry necessaryfor the device of the present embodiment is markedly smaller than thatof the conventional device.

Second Embodiment

A block diagram of a state machine in accordance with a secondembodiment of the present invention is shown in FIG. 4. The variousstates shown in FIG. 4 correspond to the states shown in FIG. 13, in asimilar manner to the embodiment shown in FIG. 1.

The device shown in FIG. 4 differs from the device shown in FIG. 1 inthat it uses JK-type F.Fs. 201-1, 201-2, . . . 201-k, . . . instead ofthe D-type F.Fs. 101-1, 101-2, . . . 101-K, . . . of FIG. 1 and it isconfigured to output further transition condition satisfying signals212W, 212Z, . . . 212Y, . . . in addition to the transition conditionsatisfying signals 111W, 111Z, . . . 111Y, . . . from a signal outputcircuit 200. Note that each of the transition condition satisfyingsignals 212W, 212Z, and 212Y becomes active when a condition fortransition to another state from the corresponding state W, state Z, andstate Y is satisfied. Within the structure of the signal output circuit200, the configuration for outputting the transition conditionsatisfying signal 212Y is as shown in FIG. 5, and comprises two ANDgates 200-1 and 200-2 and one OR gate 200-3, by way of example.

The operation of the state machine of FIG. 4 will now be described withreference to the timing chart of FIG. 6.

In a similar manner to the operation of the state machine of FIG. 1,when the transition condition satisfying signal 111Y becomes active,this means that it becomes true and is input to the D input terminal ofthe D-type F.F. 105 through the OR gate 104 of the synchronization pulsegeneration circuit 102. Since an inversion of the reference clock signal110 is being input to the C input terminal of the D-type F.F. 105, 1appears at the Q output terminal of the D-type F.F. 105 at the time b,which is the next time the reference clock signal 110 falls (theinverted signal thereof rises) after the time a (see the output signal115Q in FIG. 6). Therefore, in a similar manner to the device of FIG. 1,the synchronization pulse signal 112, which is at “1” for the width ofthe half-cycle of the reference clock signal 110, appears from the ANDgate 103 in synchronization with the reference clock signal 110 at thetime c, as shown in FIG. 6.

In this case, to the JK-type F.F. 201-k, to which the activatedtransition condition satisfying signal 111Y is input through the J inputterminal (the first input terminal) thereof, the synchronization pulsesignal 112 are also input through the C input terminal thereof duringthe period in which the transition condition satisfying signal 111Y isactive, as shown in FIG. 6. Thus a signal that makes the state Y activeis output from the Q output terminal of the JK-type F.F. 201-k at thetime c shown in FIG. 6.

The synchronization pulse signal 112 does not become activesubsequently, so long as no other transition condition satisfying signalsuch as the signal 111W becomes active, so the Y state is held by theoutput from the Q output terminal of the D-type F.F. 101-k.

Now assume in this case that the transition condition presence signal111W becomes true at the time d. At this point, a transition conditionfrom the state Y to another state becomes active simultaneously, so thetransition condition satisfying signal 212Y becomes active. Thetransition condition satisfying signal 212Y becoming active causes thegeneration of the synchronization pulse signal 112 at the time f, by thesame operation as that which activated it at the time c. Thesynchronization pulse signal 112 rises and at the time f so that thetransition condition presence signal 111W which has become active isinput to the J input terminal of the JK-type F.F. 201-1, which makes thestate machine switch to the state W.

At this point, the transition condition satisfying signal 111Y that isbeing input to the J input terminal of the JK-type F.F. 201-k isnon-active and the transition condition satisfying signal 212Y that isbeing input to the K input terminal (second input terminal) of theJK-type F.F. 201-k is active, which means that the output from the Qoutput terminal of the JK-type F.F. 201-k becomes “0” and the state Ysimultaneously becomes false.

In this manner, effects that are similar to those of the firstembodiment can be achieved even when each state holding means isconfigured of a JK-type F.F.

Third Embodiment

A circuit diagram of a state machine in accordance with a thirdembodiment of the present invention is shown in FIG. 7, with the statesobtained by the device of FIG. 7 being shown in FIG. 8.

In the third embodiment, the configuration is such that the operation ofk numbers of (where k is two in FIG. 7) flip-flops 301-1 and 301-2 isbased on k numbers of (e.g., two) combined transition-conditionsatisfying signals 311 and 312 from a signal output circuit 300 and thesynchronization pulse signal 112 from the synchronization pulsegeneration circuit 102, and the states thereof are decoded by a decoder302 in such a manner that a number of states n, which is greater than k(n is four in FIG. 7), can be created therefrom.

The signal output circuit 300 shown in FIG. 7 is configured of eight ANDgates 300-1 and 300-8 and six OR gates 300-10 to 300-15, as shown by wayof example in FIG. 9. This signal output circuit 300 makes a combinedtransition-condition satisfying signal 311 active when both a state Band the condition b are satisfied, when both a state D and the conditiond are satisfied, when the state E is satisfied but a condition e is notsatisfied, or when the state D is satisfied but the condition d is notsatisfied. The signal output circuit 300 also makes another combinedtransition-condition satisfying signal 312 active when both a state Aand the condition a are satisfied, when both the state D and thecondition d are satisfied, when the state B is satisfied but thecondition b is not satisfied, or when the state E is satisfied but thecondition e is not satisfied.

Each of the two D-type F.Fs. 301-1 and 301-2 functions as a register orstate code holder means for holding a 2-bit output (state code signal).These 2-bit outputs are a Q output from the D-type F.F. 301-1 and a Qoutput from the D-type F.F. 301-2. Any one of four states A to D (statesignals) are obtained by the decoder 302 decoding these 2-bit outputs.

In this case, if the Q output of the D-type F.F. 301-1 is R0 and the Qoutput of the D-type F.F. 301-2 is R1, the states A to D are defined asfollows:

state A=(R0, R1)=(0, 0)

state B=(R0, R1)=(0, 1)

state C=(R0, R1)=(1, 0)

state C=(R0, R1)=(1, 1)

In this manner, the third embodiment makes it possible to construct astate machine using a number of flip-flops that is smaller than thenumber of states to be held. Moreover, this third embodiment makes itpossible to reduce redundancy by making it unnecessary to have signalsfor holding the various states, in a similar manner to the first andsecond embodiments, so that the circuitry is simpler and it is alsopossible to expect a reduction in the number of debugging andmaintenance steps. Note that one of the JK-type flip-flops of the secondembodiment can be used instead of the D-type flip-flops in this thirdembodiment. In such a case, the signal output circuit 300 generates andoutputs a combined transition-condition satisfying signal for the Jterminal (first input terminal) and another combinedtransition-condition satisfying signal for the K terminal (second inputterminal) respectively.

Regardless of the type of flip-flop used, this third embodiment issimilar to the first and second embodiments in that the synchronizationpulse signal is generated only when a transition condition is satisfied,and thus the power consumption thereof can be reduced.

Note that, although the outputs from Q output terminals are mentioned asthe outputs from the various flip-flops used in the above first to thirdembodiments, inverted output signals from /Q output terminals thereofcould also be used therefor.

Fourth Embodiment

A block diagram of a fourth embodiment of the present invention is shownin FIG. 10. This state machine comprises a state-monitoring section1001, a transition control section 1002, and a state holding section1003. The transition control section 1002 generates a transitioncondition satisfying signal 1012 based on an abnormality detectionsignal 1010 and an input signal 1011. The state holding section 1003 isprovided with state holding means and synchronization pulse signalgeneration means as described in the first to third embodiments, and itholds the transition condition satisfying signal 1012 based on thesynchronization pulse signal, then makes any one of n numbers of statesignals 1013 active (true) for output.

The state-monitoring section 1001 monitors n numbers of states and isprovided with abnormality detection means which determines that it isnormal when only one of the n numbers of states is true, but which viewsany other cases as an abnormality. If an abnormality is detected by theabnormality detection means, the state-monitoring section 1001 outputsthe abnormality detection signal 1010 to the state holding section 1003.The state holding section 1003 sets the state machine to a prescribedstate other than the abnormal state, for example, resetting the statemachine to the state immediately after the power is turned on, inaccordance with the abnormality detection signal 1010.

An example of the logic of abnormality detection when there are fourstates A to D is given by the following equation:

AB+AC+AD+BC+BD+CD+not(A+B+C+D)  (1)

If Equation 1 is true, this indicates that either none of the states Ato D is true or two or more states are true. Assume that the abnormalitydetection means has detected an abnormality when the abnormalitydetection logic is true. Note that the logic of abnormality detection isnot limited to Equation 1; other logical equivalence can well be used.In this case, Equation 1 refers to a case in which there are four statesA to D, but it can also be extended and applied to any number of statesn.

By configuring the state machine in this manner, it is possible todetect an abnormal state caused by incorrect operation and return thestate machine to its correct state.

Fifth Embodiment

A block diagram of a fifth embodiment of the present invention is shownin FIG. 11. A semiconductor device 1101 in accordance with the fifthembodiment comprises state machines 1102 to 1106. These state machines1102 to 1106 input and output input-output signals 1112, based onreference clock signals 1110 and 1111. All or some of these statemachines 1102 to 1106 have the configuration described above withreference to the first to fourth embodiments.

The state machines 1102 to 1106 operate in synchronization with thereference clock signals 1110 and 1111 and determine the state of asignal within an (m+1)th operating cycle based on the state of thesignal within an mth operating cycle.

Since redundancy in the thus configured semiconductor device can bereduced by making it unnecessary to input a holding condition to aflip-flop that is a state holding means in all or some of the statemachines, the circuitry is simplified and the effect of reducing thenumber of debugging and maintenance steps can be achieved. In addition,power consumption in all or some of the state machines can be reducedbecause the synchronization pulse signal is generated only when atransition condition is satisfied.

A further embodiment of the present invention relates to electronicequipment comprising a semiconductor device. Electronic calculators, byway of example, include a plurality of semiconductor devices asstructural requirements, and many sections thereof operate insynchronization with each other. A protocol control device such as a LANconnection device has a semiconductor device comprising a large numberof state machines. If the present invention is applied to all or some ofthe semiconductor devices in such electronic devices, the effects of thepresent invention within each of the semiconductor devices act insynergy, so that the cumulative effect achieved by the entire electronicdevice is greater.

What is claimed is:
 1. A state machine operating in synchronization witha reference clock signal and holding any one state that shifts between nnumbers of states, said state machine comprising: signal output meansfor activasting and outputting any one of n numbers of transitioncondition satisfying signals, every time a condition for transition toany of said n numbers of states is satisfied; n numbers of state holdingmeans provided in correspondence to said n numbers of states, foroutputting n numbers of state signals representing the corresponding nnumbers of states, any one of said n numbers of state signals beingactivated so as to hold one of said n numbers of states; andsynchronization pulse signal generation means for generating a one-shotsynchronization pulse signal which synchronizes with said referenceclock signal, when said condition for transition to any one of saidstates is satisfied, wherein said one-shot synchronization pulse signalis input in common to all of said n numbers of state holding means, andany one of said state holding means corresponding to any one said statesfor which a transition condition is satisfied makes corresponding one ofsaid state signals active, during a period from the satisfaction of saidcondition for transition to one of said states until the satisfaction ofa condition for transition to another one of said states.
 2. The statemachine as defined in claim 1, wherein: said n numbers of state holdingmeans are configured of first to nth D-type flip-flops; said n numbersof transition condition satisfying signals are input to data inputterminals of said corresponding first to nth D-type flip-flops; saidsynchronization pulse signal generated by said synchronization pulsesignal generation means is input to clock input terminals of said firstto nth D-type flip-flops; and first to nth state signals are output fromdata output terminals of said corresponding first to nth D-typeflip-flops.
 3. The state machine as defined in claim 1, wherein: said nnumbers of state holding means are configured of first to nth JK-typeflip-flops; said n numbers of transition condition satisfying signalsare input to data input terminals of said corresponding first to nthJK-type flip-flops; signals any one of which is made active bysatisfying a condition for transition to another state from any one ofsaid first to nth states are input to second input terminals of saidfirst to nth JK-type flip-flops; said synchronization pulse signalgenerated by said synchronization pulse signal generation means is inputto clock input terminals of said first to nth JK-type flip-flops; andfirst to nth state signals are output from data output terminals of saidcorresponding first to nth JK-type flip-flops.
 4. The state machine asdefined in claim 1, wherein: said synchronization pulse signalgenerating means comprises a D-type flip-flop and an AND circuit; asignal that is made active by satisfying a condition for transition toany of said n numbers of states is input to a data input terminal ofsaid D-type flip-flop; an inverted signal of said reference clock signalis input to a clock input terminal of said D-type flip-flop; and a Qoutput of said D-type flip-flop and said reference clock signal areinput to said AND circuit.
 5. The state machine as defined in claim 1,further comprising: state-monitoring means for detecting an abnormalityby monitoring said n numbers of states and detecting an abnormality thatis indicated by at least two states being true.
 6. The state machine asdefined in claim 5, wherein: after detecting an abnormality, saidstate-monitoring means resets said abnormal state and sets the statemachine to a normal state.
 7. The state machine as defined in claim 6,wherein: after detecting an abnormality, said state-monitoring meansresets said abnormal state and sets the state machine to an initialstate.
 8. A state machine operating in synchronization with a referenceclock signal and holding any one state that shifts between n numbers ofstates, said state machine comprising; signal output means foroutputting k numbers of (where k<n) first to kth combinedtransition-condition satisfying signals corresponding to said n numberof states, every time there is a change in conditions for transition toany of said n numbers of states; synchronization pulse signal generationmeans for generating a one-shot synchronization pulse signal whichsynchronizes with said reference clock signal when said condition fortransition to one of said states is satisfied; k numbers of state codeholder means for outputting first to kth state code signalscorresponding to said first to kth combined transition-conditionsatisfying signals, based on said first to kth combinedtransition-condition satisfying signals and said one-shotsynchronization pulse signal; and decoding means for decoding said firstto kth state code signals that are output from said k numbers of statecode holder means and generating n numbers of state signalscorresponding in a one-to-one manner to said n numbers of states.
 9. Thestate machine as defined in claim 8, wherein: said k numbers of statecode holder means are configured of first to kth D-type flip-flops; saidfirst to kth combined transition-condition satisfying signals are inputto data input terminals of said corresponding first to kth D-typeflip-flops; said synchronization pulse signal generated by saidsynchronization pulse signal generation means is input to clock inputterminals of said first to kth D-type flip-flops; and said first to kthstate code signals are output from data output terminals of saidcorresponding first to kth D-type flip-flops.
 10. The state machine asdefined in claim 8, wherein: said k numbers of state code holding meansare configured of first to kth JK-type flip-flops; said first to kthcombined transition-condition satisfying signals are input respectivelyto a first input terminal and a second input terminal of thecorresponding first to kth JK-type flip-flops; said synchronizationpulse signal generated by said synchronization pulse signal generationmeans is input to clock input terminals of said first to kth JK-typeflip-flops; and said first to kth state code signals are output fromdata output terminals of said corresponding first to kth JK-typeflip-flops.
 11. The state machine as defined in claim 8, wherein: saidsynchronization pulse signal generating means comprises a D-typeflip-flop and an AND circuit; a signal that is made active by any ofsaid first to kth combined transition-condition satisfying signals isinput to a data input terminal of said D-type flip-flop; an invertedsignal of said reference clock signal is input to a clock input terminalof said D-type flip-flop; and a data output of said D-type flip-flop andsaid reference clock signal are input to said AND circuit.
 12. The statemachine as defined in claim 8, further comprising: state-monitoringmeans for detecting an abnormality by monitoring said n numbers ofstates and detecting an abnormality that is indicated by at least twostates being true.
 13. The state machine as defined in claim 12,wherein: after detecting an abnormality, said state-monitoring meansresets said abnormal state and sets the state machine to a prescribedstate other than said abnormal state.
 14. The state machine as definedin claim 13, wherein: said state-monitoring means resets said abnormalstate and sets the state machine to an initial state.
 15. Asemiconductor device operating in synchronization with a reference clocksignal, such that a state of a signal in an (m+1)th operating cycle isdetermined based on a state of a signal within an mth operating cycle,wherein said semiconductor device comprises n numbers of state machines,and at least one state machine is configured of the state machine asdefined in claim
 1. 16. Electronic equipment comprising thesemiconductor device defined in claim 15.